This invention relates to a method of fabricating semiconductor devices and more specifically to a planarization process for use during the fabrication of semiconductor devices.
Very Large Scale Integrated (VLSI) and Ultra Large Scale Integration (ULSI) circuits utilize a variety of devices having different feature sizes or device dimensions. Such devices include, but are not limited to, transistors, diodes, capacitors, resistors and wires. The minimum state of the art device dimensions have shrunk to the submicron level. Some devices may have submicron feature sizes while others may simultaneously have much greater feature sizes. Shallow trenches of constant height and varying widths are used to isolate individual devices. These trench widths can vary greatly. These trenches are typically filled with a dielectric material, such as silicon oxide. Because of the complex topography, especially when shallow trenches of greatly varying widths are used, a problem often encountered is achieving a uniform oxide fill, in those trenches, independent of trench size and device density. For such VLSI and ULSI circuits, topology management during fabrication has become a critical process step.
As feature sizes or device dimensions are scaled downward, more stringent requirements on deposition, photo, and etching processing are posed. Surface-clearing planarization processes, such as are used to create oxide-filled trench isolation, often require that the planarized material thickness be controlled to within a very tight tolerance. When simultaneously achieved over all topographies this condition is referred to as "global" planarization.
As compared to conventional Local Oxidation of Silicon (LOCOS) isolation, shallow trench isolation (STI) offers improved isolation between devices and greater packing density. Additionally STI offers a higher degree of planarity, which becomes increasingly important as the photolithographic depth of focus budget continues to shrink with decreasing minimum line width.
A common method for planarizing shallow trenches is a combined resist etch-back (REB)/chemical mechanical polish (CMP). This combined REB/CMP process sequence is as follows. The isolation trenches are patterned onto a semiconductor wafer or substrate, generally a silicon substrate. Oxide is deposited conformally onto the wafer with patterned trenches. Photoresist filler blocks then are patterned into the gaps above the trenches. A second resist layer then is coated onto the wafer to create a relatively planar surface. The filler blocks prevent resist from flowing down into the depressions above the trenches, reducing variations in resist thickness across various active area and trench dimensions. This provides a relatively planar surface for the subsequent etch-back. The wafer then is etched, leaving a small amount of oxide on the active areas. Finally, CMP is used to polish the oxide back to the silicon nitride that caps the active area mesas. However, this REB/CMP process is pattern-dependent. During the REB step, small active areas adjacent to trenches that are too small to receive a resist filler block (due to photolithographic tolerances), but too large to fill during oxide deposition, will have less resist than large active areas. Therefore, these small active areas will have less oxide following the etch. With regard to CMP, the small isolated active areas will polish faster than large dense active areas. These adverse pattern effects are well known. Dishing, an undesirable polishing of oxide in wide trenches due to polishing pad deformation, also will occur during the CMP step. The result of these pattern dependencies is that the silicon nitride thickness will vary significantly across various feature sizes following the REB/CMP process, adversely impacting final planarity.
Another method to obtain better planarization of a silicon wafer is to utilize three resist layers. This is accomplished by depositing a conformal oxide onto the silicon wafer followed by patterning filler resist blocks and coating a second resist layer, similar to the two resist layer process previously described above. The second resist layer is etched back to the conformal oxide, and then a third resist layer is applied. This method produces better planarization than the conventional two resist layer method described above. However, some variation in oxide thickness will still exist. Further, the additional etch and coat steps reduce the process window due to accumulated non-uniformities.
Accordingly, although various improvements in planarization techniques have been developed, manufacturability problems still exist related to final nitride thickness variation between isolated and dense areas as well as non-uniform resist coat and etch-back.